1. Field of the Invention:
The invention relates generally to a clock generator, and more specifically, to an adjustable duty cycle clock generator employing a single delay line and multiplexer means to selectively adjust the high and low times of a generated clock signal, particularly useful in latch based logic designs.
2. Description of Related Art
By way of background, most non-combinational logic designs broadly fall into one of two categories namely: flip/flop based designs or latch based designs. While most application specific integrated circuits (ASIC) fall under the flip/flop based design category, high performance circuits generally rely on latch based designs.
A flip/flop based design and its limitations are best understood with reference to FIG. 3 and the description given hereinbelow. A flip/flop register 10 includes a first D-type latch 12 cascaded with a second D-type latch 14. The first D-type latch 12 has its D-input coupled to the input data, its clock input to the input clock signal (i.e. the .phi.1 clock) and its output to the D-input on the second D-type latch 14. The second D-type latch 14 has its clock input coupled to the inversion of the .phi.1 clock (i.e. the .phi.2 clock) and its output supplies the latched data. The double clocking by .phi.1 and .phi.2 is performed, for the most part, to decouple speed paths and to prevent metastable conditions from occurring between the input data and the latched data output. It can be seen therefore, that the latched data output cannot change except at the rising edges of .phi.2 clocks. Thus the speed to which a synchronous flip/flop design can operate is limited by the propagation delay through the combinational logic between flip/flops during one clock period. The speed is independent of the duty cycle of the clock.
A latch based design is similar to a flip/flop based design except that the latched data output is split into two data paths which are made available either on the .phi.1 or .phi.2 clock. This approach is used in high performance microprocessor designs as an expedient to obtain advantages in speed, circuit element reduction, and power conservation. Speed improvement occurs since different operations may be performed during each clock phase. For example, a programmable logic array (PLA), random access memory (RAM), or address/data bus may be precharged during one clock phase, then accessed during the next clock phase. Circuit element reduction occurs since fewer D-type latches are needed. Power consumption is reduced because a so-called "conditional" or "gated clock" latch can be constructed, inhibiting the unnecessary clocking of latches when input data has not changed or is irrelevant.
By way of example, an exemplary conditional data latch is depicted in FIG. 4 illustrating a "gated" .phi.2 clock. A first D-type latch 16 is clocked by .phi.1 and has its latched output coupled to a cluster of combinational logic 18 which generates a first term to a first input on logic AND gate 20. A second input on AND gate 20 is coupled to the .phi.2 clock which is usually the inversion of the .phi.1 clock. The output of AND gate 20 generates a "gated" clock signal to a clock input on a second D-type latch 22 whose data input may originate from the cluster of combinational logic 18, another cluster of combinational logic (not shown), or another .phi.1 or .phi.2 latch (not shown).
Along with the advantages of a conditional latch based design however, are the attendant problems associated with commingling combinational and latch based logic. For example, the delay of the cluster of combinational logic 18 can cause the AND gate 20 to miss or generate a false gated .phi.2 clock signal. This point is best illustrated with reference to the timing diagram in FIG. 5. As depicted in FIG. 5, the output of latch 16 (Q.sub.16) goes high in response to the input D.sub.16 being high and the rising edge of the .phi.1 clock. Q.sub.16 then stimulates combinational logic 18 to produce the first input (O.sub.18) to AND gate 20. O.sub.18 is usually delayed a time (t) later than Q.sub.16 due to gate delays associated with combinational logic 18. If t is too large and O.sub.18 is switching low as depicted in FIG. 5, AND gate 20 will temporarily go high at the rising edge of the .phi.2 clock, and consequently, latch 22 will be updated on a cycle that it should have held its previous state. Ostensibly, this situation cannot be tolerated for a reliable design.
In an attempt to ameliorate this problem, logic designers have either imposed a minimum period on the .phi.1 and .phi.2 clocks (i.e. limited the frequency) to augment the safety margin between .phi.1 and .phi.2 rising edges or have reduced the amount of delay time (t) induced by combinational logic 18. Unfortunately, limiting the operating frequency of the .phi.1 and .phi.2 clocks results in limited or poor performance. Similarly, reducing the amount of delay time (t) induced by combinational logic 18 is limited by the amount of functionality sought and the process technology used to fabricate the combinational logic 18.
By way of further background, in previous latch based designs, much emphasis was placed on de-skewing the generated clock from the source clock and on maintaining a 50% duty cycle. The notion of a 50% duty cycle for .phi.1 and .phi.2 was that the data set-up time could be equally shared between .phi.1 to .phi.2 latch transfers and .phi.2 to .phi.1 latch transfers. Generally speaking however, time delays are not evenly distributed between .phi.1 to .phi.2 and .phi.2 to .phi.1 data paths. Consequently, using a 50% duty cycle clock generally results in a lower than obtainable operating frequency since the clock speed must take into account the worst case speed path, thus leaving slack in the clock phase which does not contain the worst case speed path.
Accordingly it can be seen from the foregoing that without jeopardizing reliability, it is desirable to maximize the clock speed for a latch based design without sacrificing functionality.